Like latches, mutexes are associated with a memory structure or a memory structure piece. But, as shown back in Figure 3-2, latches are truly separate from their associated memory structures. While latch and mutex serialization objectives are the same, kernel developers can define a mutex to be part of the underlying memory structure or memory structure piece. This allows for increased memory structure granularity, with less concurrency control overhead and less false contention. If the mutex is defined as part of the memory structure or memory structure piece, and the memory structure is deallocated, then so is the mutex. For example, a mutex can be defined for each cursor. Oracle could also define a mutex for not only the parent cursor, but also any and all related cursors or cursor parts.

Oracle's flexible mutex implementation comes in very handy for extremely complex memory structures, like Oracle's library cache. When using a library cache latch, Oracle kernel code developers must associate multiple memory pieces with one of the library cache latches. Because library cache memory structures are highly interconnected, Oracle's latching capabilities result in a practical limitation (performance and coding complexity) as to how granularly the latches can be applied.

The unintentional result is known as false contention. This unfortunate situation occurs when two processes require access to different memory pieces, yet both memory pieces are controlled by the same latch. Figure 3-14 shows an example of false contention. Process P100 requires access memory structure MS1. Process P200 requires access to memory structure MS2. A single latch CS999 controls access to both memory structures MS1 and MS2. If process P100 has latch CS999 while accessing MS1, process P200 will contend for the latch, even though it has no need to access memory structure MS1! Because the processes are contending for the same control structure, yet will not access the same memory structure, they are falsely contending. The more complex the underlying memory structure, the more likely this will occur.